1. Field
The disclosed invention relates to manufacturing of silicon carbide (SiC) crystals and wafers.
2. Related Art
Silicon carbide, SiC, is a crystalline semiconductor material, recognized by those familiar with materials science, electronics and physics as being advantageous for its wide band gap properties and also for extreme hardness, high thermal conductivity and chemical inert properties. These properties make SiC a very attractive semiconductor for fabrication of power semiconductor devices, enabling power density and performance enhancement over devices made from more common materials like silicon.
The most common forms of SiC consist of cubic or hexagonal arrangements of atoms. The stacking of Si and C layers can take on many forms, known as polytypes. The type of silicon carbide crystal is denoted by a number denoting the number of repeat units in the stacking sequence followed by a letter representing the crystalline format. For example the 3C-SiC polytype refers to a repeat unit of 3 and a cubic (C) lattice, while a 4H-SiC polytype refers to repeat unit of 4 and a hexagonal (H) lattice.
The different silicon carbide polytypes have some variations in materials properties, most notably electrical properties. The 4H-SiC polytype has the relatively larger bandgap while the 3C-SiC has a smaller bandgap, with the bandgaps for most other polytypes falling in between. For high performance power device applications when the bandgap is larger, the material is more capable, in theory, to offer relatively higher power and thermal conductivity performance.
SiC crystals do not occur in nature and as such must be synthesized. Growth of SiC crystals can be executed by sublimation/physical vapor transport or chemical vapor deposition.
Growth of SiC by sublimation is very challenging. Temperatures in excess of 2,000° C. are required to generate vapor stream of Si/C species by sublimation, which places great limitations on the reaction cell components and the furnace design. Originally SiC abrasive materials formed by processes like the Acheson method were used as the source of the Si and C atoms for the crystal, and as the technology matured groups developed means to synthesize SiC source powder specifically for SiC crystal growth. The growth is usually performed in a graphite container within a vacuum chamber. The graphite container is heated by either resistive methods or induction methods. The container is insulated in a careful manner so as to create controlled temperature gradients within the volume. A seed crystal is used, which is usually shaped like a plate or disc. The seed crystal is typically oriented with its growth surface facing the source material. The location of the seed crystal in the container is designed such that when the container is heated, the seed is at a relatively lower temperature position, while the Si—C source materials are at the higher temperature position. When the container is heated to a temperature sufficient to sublime the source material, the vapors will travel towards the low temperature region and condense on the seed crystal. While this appears simple in concept, in practice the growth of SiC is very complicated and recognized by those who practice as very difficult to perform.
Historically, initial progress in SiC sublimation-based crystal growth is described first by Lely (U.S. Pat. No. 2,854,364) whose method of unseeded crystal growth resulted in small hexagonal SiC platelets. In the 1970s and 1980s the art to produce the first crystals of size attractive for producing devices was done in Russia by Tairov and Tsvetkov (Journal of Crystal Growth, 52 (1981) p. 146-50 and Progress in Controlling the Growth of Polytypic Crystals in Crystal Growth and Characterization of Polytype Structures, P. Krishna, ed., Pergammon Press, London, p. 111 (1983)). Their approach used a Lely crystal as a seed, and conducted growth by sublimation and transport as described above. These results showed methods for polytype control by choice of seeds, pressure control and temperature gradients. Later, Davis (U.S. Pat. No. 4,866,005) revealed improvements by judicious selection of source materials and gradient controls. Refinements on the methods of Tairov, Tsvetkov and Davis continue to be revealed to this day.
When methods to produce larger crystals emerged, focus also moved to control defects in the crystals. Defects can be categorized as inclusions and crystal dislocations. The primary crystalline defects in SiC crystals are screw dislocations. Among these are a special case known as a micropipe or hollow core screw dislocations. Additionally, there are basal plane dislocations and threading edge dislocations. These defects originate from many sources. For example, defects contained in the seed crystal can be passed to the newly grown crystal volume. Stresses arising from temperature gradients and thermal expansion mismatch and imparted to the seed and the crystal during growth can result in formation of dislocations. Deviation of the stoichiometry in the sublimation vapor stream from that needed to form SiC can result in unstable polytype growth; in turn leading to polytype inclusions in the grown crystal, which leads to dislocation formation at the polytype boundaries. Even interactions between dislocations can create or eliminate dislocations.
SiC crystals produced by methods identified have large concentrations of dislocations. As of this filing, the commonly reported values of screw dislocation and basal plane concentration are nominally 5,000-10,000/cm2, respectively. The dislocations are most commonly assessed by sectioning the crystal in the plane normal to the crystal axis of symmetry. Etching the exposed crystal surface with molten salt, like potassium hydroxide, at temperatures in the 350-500° C. range will reveal the dislocations. Each dislocation type has a unique shape so they can be uniquely counted. The dislocations are commonly counted and reported as a number divided by the inspection area. This characterization method is useful as it allows for easy correlation of defects contained in planar semiconductor devices formed on the crystal plane. There are many examples in the literature which show that dislocations are not uniformly distributed in the plane of observation. The large count of dislocations makes it very impractical to count every single one, especially as today inspections can be required on sections greater than or equal to the equivalent of 100 mm diameter circles. So the etched area is sampled to determine the amount of dislocations. Incorrect sampling methods can lead to errors in the estimation of the dislocation concentration associated with larger crystals. In most reports, the details of the sampling method are not provided, so replication of reported results can often be difficult, if not impossible.
Scientists experienced in solid state physics and semiconductor devices know that dislocations result in device performance below the theoretical properties of the material. Therefore, modern effort focused on improvements of semiconductor SiC crystal quality look to identify and control the factors which can reduce defects originating in crystal growth.
Once large enough crystals are produced, the crystal must be cut and fabricated into wafers in order to be useful to fabricate semiconductor devices using planar fabrication methods. As many semiconductor crystals (e.g., silicon, gallium arsenide) have been successfully developed and commercialized into wafer products, the methods to fabricate wafers from bulk crystals are known. A review of the common approaches to, and requirements for wafer fabrication and standard methods of characterization, can be found in Wolf and Tauber, Silicon Processing for the VLSI Era, Vol. 1—Process Technology, Chapter 1 (Lattice Press—1986).
Due to its hardness, fabrication of SiC into wafer substrates presents unique challenges compared to processing other common semiconductor crystals like silicon or gallium arsenide. Modifications must be made to the machines and the choices of abrasives changed beyond commonly used materials. It has been reported that substantial subsurface damage is observable on mirror polished SiC wafers, and this can be reduced or removed by using chemical enhanced mechanical polishing methods similar to that used in the silicon industry (Zhou, L., et al., Chemomechanical Polishing of Silicon Carbide, J. Electrochem. Soc., Vol. 144, no. 6, June 1997, pp. L161-L163).
In order to build semiconductor devices on SiC wafers additional crystalline SiC films must be deposited on the wafers to create the device active regions with the required conductivity value and conductor type. This is typically done using chemical vapor deposition (CVD) methods. Techniques for growth of SiC by CVD epitaxy have been published from groups in Russia, Japan and the United States since the 1970's. The most common chemistry for growth of SiC by CVD is a mixture of a silicon containing source gas (e.g., monosilanes or chlorosilanes) and a carbon containing source gas (e.g., a hydrocarbon gas). A key element to growth of low defect epitaxial layers is that the substrate surface is tilted away from the crystal axis of symmetry to allow the chemical atoms to attach to the surface in the stacking order established by the substrate crystal. When the tilt is not adequate, the CVD process will produce three dimensional defects on the surface, and such defects will result in non-operational semiconductor devices. Surface imperfections, such as cracks, subsurface damage, pits, particles, scratches or contamination will interrupt the replication of the wafer's crystal structure by the CVD process (see, for example, Powell and Larkin, Phys. Stat. Sol. (b) 202, 529 (1997)). It is important that the polishing and cleaning processes used to fabricate the wafer minimize surface imperfections. In the presence of these surface imperfections several defects can be generated in the epitaxial films including basal plane dislocations and cubic SiC inclusions (see for example, Powell, et. al. Transactions Third International High-Temperature Electronics Conference, Volume 1, pp. II-3-II-8, Sandia National Laboratories, Albuquerque, N. Mex. USA, 9-14 Jun. 1996).
Defects in SiC are known to limit or destroy operation of semiconductor devices formed over the defects. Neudeck and Powell reported that hollow core screw dislocations (micropipes) severely limited voltage blocking performance in SiC diodes (P. G. Neudeck and J. A. Powell, IEEE Electron Device Letters, vol. 15, no. 2, pp. 63-65, (1994)). Neudeck reviewed the impact of crystal (wafer) and epitaxy originated defects on power devices in 1994, highlighting limitations of power device function due to screw dislocations and morphological epitaxy defects (Neudeck, Mat. Sci. Forum, Vols. 338-342, pp. 1161-1166 (2000)). Hull reported shift to lower values in the distribution of high voltage diode reverse bias leakage current when the diodes were fabricated on substrates having lower screw dislocation density (Hull, et. al., Mat. Sci. forum, Vol. 600-603, p. 931-934 (2009)). Lendenmann reported forward voltage degradation in bipolar diodes was linked to basal plane dislocations in the epilayer that originate from basal plane dislocations in the substrate (Lendenmann et. al., Mat. Sci. Forum, Vols. 338-342, pp. 1161-1166 (2000)).
Modern technology for growth of 4H-SiC crystals has not been successful to develop a commercial method for a crystal growth process that allows simultaneous control over the gamut of dislocation types.
Various methods disclosed in the prior art are often lacking in details regarding the specific steps employed in the crystal growth or the methods employed to assess the concentration of defects and demonstrate repeatability.
In recent years, it has become desirable to grow larger crystals as silicon carbide and gallium nitride as such materials which are useful in building high efficiency power/RF diodes and transistor devices. However, large bulk crystals of silicon carbide (SiC) are difficult to grow, in part because such processes require high temperatures of up to 2,500° C. Currently, most growth processes utilize vapor-based transport methods such as physical vapor transport (PVT) sublimation methods.
For example, crystals of SiC may be grown by PVT in a reaction cell which is typically formed from solid graphite. The cell is typically a right angle cylinder and the grade of graphite is chosen so that its thermal expansion coefficient is close to that of SiC in order to minimize stresses imparted by the differences in the respective coefficients of expansion. The SiC seed crystal is typically provided in a disk shape. The seed crystal is polished and can be coated on the side opposite the growth surface with a material which is stable at the growth temperatures. The presence of a protective carbon coating can help to suppress deterioration of the seed during the crystal growth process, as voids (“thermal evaporation cavities”) may form in the seed when the protection is absent.
The seed is generally oriented in the reaction cell so that the major axis of the cylindrical reaction cell and the plane of the seed wafer are nominally at right angles to each other. In most PVT reaction cells, the seed crystal is placed above the Si/C source feedstock to aid in controlling vapor flow as well as keeping the seed free of debris and contamination during growth. In this type of PVT reaction cell arrangement, the seed is typically supported above the vapor source by rigid or mechanical attachment of the seed to the lid of the reaction cell. The seed may be attached to the lid by adhesive, cement, retaining rings, and the like. However, the act of mounting the seed to the reaction cell lid or seed holder can lead to undesirable effects during crystal growth.
For example, during the mounting process, scratching of the coated seed back may occur. In addition, a void may be created between the seed and reaction cell ceiling interface during the mounting process. Such occurrences may exacerbate formation of evaporation cavities of the seed backside, resulting in defect formation. Moreover, differences in thermal expansion between the seed and lid can cause stresses in the seed. See, for example, discussion in Japanese patent publication JP 2011-20860.
It is important to support the seed crystal in the reaction cell in a position where the temperature can be controlled to allow condensation of the vapor stream on the seed surface. However, because the reaction cell is typically made from a different material than the seed crystal, the rigid attachment methods often create stresses in the crystal during growth. For example, when the seeds are mounted to the reaction cell or lid using an adhesive, it is possible for the seed to be bent during the mounting process, which results in undesirable stress in the crystal.
As a result, attempts have been made to develop alternative methods for supporting the seed crystal during growth. For example, JP 2011-20860 relies on pressure differentials to create vacuum that holds the seed against the lid. However, contact between the crystal and holder is such that stress on the crystal may still occur during growth. Specifically, pressure differential forces may deform the seed. Moreover, if the lid's surface is not smooth and flat, it will create pressure points on the back surface of the seed, thereby generating strains in the seed. Similarly, any particulate material that may inadvertently be captured between the seed and the lid would create pressure point. Even if the lid is perfectly flat such that the seed perfectly contacts the lid, when seed touches the lid it will cool the backside of the seed, causing it to bow away from the lid and the seal will be broken. Also, the bowing will cause the crystal to be in stress, leading to defects in the growing crystal.
There are other problems with the approach disclosed in the JP 2011-20860. For example, when the seed is elevated due to pressure differential, it blocks gas flow out of the crucible, thus leading to increased pressure and temperature inside the crucible. At least for these reasons it is preferred to maintain the flow of gas out of the crucible. Also, as the crystal grows it gets heavier and at some point will be too heavy for the pressure differential to maintain it against the lid, at which point the crystal would drop, leading to sudden change in the temperature of the crystal and due to resumed flow of gas out of the crucible, reduced pressure and temperature inside the crucible.
Accordingly, there is a need in the art for a method of SiC crystal growth, which results in crystal growth with minimized stress resulting in reduced defects such as micropipes, screw dislocations and basal plane dislocations.